Ph. D. in Computer Science from Indian Statistical Institute, Kolkata, India, February, 2011; Thesis Title: Fast Placement and Floorplanning Methods in Modern Reconfigurable FPGAs.
Master of Computer Science from Interdisciplinary School of Scientific Computing, University of Pune, 1998. (I st Division Distinction with 75.8% marks).
Bachelor of Computer Science from Fergusson College, under University of Pune, 1996. (I st Division Distinction with 76.25% marks).
Higher Secondary from Tamil Nadu Board of Higher Secondary Education, 1993. (with 90.0% marks) 5. Madhyamik from West Bengal Board of Secondary Education, 1991. (I st division with 78.5% marks)
Received Student Innovative Potential Award 2011 from Indian National Academy of Engineering (INAE) for the Ph. D Thesis titled Fast Placement and Floorplaning Methods in Modern Reconfigurable FPGAs
Received National Scholarship for Madhyamik Exam (After class X), 1991
List of Publications:
Pritha Banerjee, Megha Sangtani and Susmita Sur-Kolay,“Floorplanning for Partially Reconfigurable FPGAs”, IEEE Trans. on Computer Aided Design of Integrated circuits and Systems, vol. 30, no. 1, pp. 8-17, January 2011.
Pritha Banerjee, Debasri Saha and Susmita Sur-Kolay,“ Cone-based placement for Field Programmable Gate Arrays”, IET Computer and Digital Techniques, vol. 5, issue 1, pp. 49-62, January 2011.
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu, Sandip Das, Subhas C. Nandy and Subhasis Bhattacharjee, “FPGA Placement using Space Filling Curves: Theory Meets Practice”, Special issue on Configuring Algorithms, Processes and Architecture (CAPA) in ACM Transactions on Embedded Computing System (TECS), vol. 9, no. 2, Article no. 12, pp. 1-23, October 2009.
Pritha Banerjee, Susmita Sur-Kolay and Arijit Bishnu, “Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs”, IEEE Trans. on Computer Aided Design of Integrated circuits and Systems, vol. 28, no. 5, pp. 651-661, May 2009.