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Watermarking in hard intellectual property for pre-fab and post-fab verification
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 23
Issue: 5
Pages: 801 - 809
A manufacture-ready layout is vulnerable to misappropriation when it is either fabricated as a chip in a fabrication facility, or reused in a system-on-chip house. We propose an intellectual property protection (IPP) scheme IPPMRL for protection of manufacture-ready layout against unauthorized reuse and inclusion of Trojans. The IPPMRL inserts watermarks in the layout according to designer's signature with an effect of tuning the delays at selected scan flip-flops. Certain dummy fills are reoriented in the neighborhood of selected net segments and it causes fine tuning of delay; certain other selected net segments are resized for coarse change in delay. The IPPMRL not only verifies the watermark in the layout, but also captures its effect as delay fault-induced responses from the packaged chips, fabricated from the watermarked layout, by applying a faster test clock. Due to the controlled effect of watermarking on delay, responses are resilient against process and temperature variation, but capable of detecting hardware Trojan. The method is adaptive to device aging. The results for ISCAS'85 and ISCAS'89 benchmark circuits show that the overhead of watermarking on circuit delay is less than 0.05% and the probability of true false or false true can be at most ∼ 10-6. © 2015 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Very Large Scale Integration (VLSI) Systems
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo