In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications, such as transconductance g m, transconductance-to-drive current ratio g m/I D, drain resistance R O, intrinsic gain, and unity-gain cutoff frequency f T, are studied for DG n-TFET, with the help of a device simulator, and compared with that for a similar DG n-MOSFET. Although g m is lower, g m/I D is found to be higher in TFET, except for small values of the gate overdrive voltage, indicating that a TFET can produce higher gain at the same power level than a MOSFET. An extremely high R O and, hence, a high intrinsic gain are also observed for a TFET as compared with that for a MOSFET. A complementary TFET amplifier is found to have more than one order of magnitude higher voltage gain than its MOS counterpart. It is also demonstrated that the drain resistance and, hence, the device gain significantly degrade for increasing body thickness of a TFET. © 2006 IEEE.

AVIK CHATTOPADHYAY

Radio Physics and Electronics

ABHIJIT MALLICK

Electronic Science

University of Calcutta (informally known as Calcutta University or CU) is a collegiate public state university located in Kolkata, West Bengal, India.&nbsp;Within India it is recognized as a &quot;Five-Star University&quot; and accredited &quot;A&quot; Grade by National Assessment and Accreditation Council.

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The University of Calcutta has secured the Fifth position among the Universities of India in the prestigious &quot;Indian University Ranking 2019&quot; list, released by the NIRF of the Ministry of Human Resource Development, Government of India.

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It was established on 24 January 1857, and was one of the first institutions in Asia to be established as a multidisciplinary and Western-style university. Its alumni and faculty include several heads of state, heads of government, social reformers, prominent artists, only academy award winner and Dirac medal winner in India, many Fellows of the Royal Society and five Nobel laureates as of 2019 which is highest in South Asia.

University Of Calcutta

Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

IEEE Transactions on Electron Devices

In this paper, a detailed investigation of the effects of varying dielectric constant of the gate dielectric on the analog performance of a tunnel FET is reported. Variation in gate dielectric constant is made for both constant physical thickness and constant effective oxide thickness (EOT). A high-k gate dielectric is found to yield improved analog performance when physical thickness is kept constant, which is due to increased gate capacitance. On the other hand, a low-k gate dielectric delivers better analog performance when EOT is kept constant. © Springer Nature Switzerland AG 2019.

Springer Proceedings in Physics

Effect of gate dielectric material on the analog performance of a ge-source tunnel fet

It is well-established that a tunnel field-effect transistor (TFET) may or may not show a good drain current saturation in its output characteristics, depending upon its device structure. In this paper, we report for the first time a new phenomenon in double-gate silicon TFETs, which causes a sudden increase in its drain current at larger drain voltages, independent of whether they show a good output current saturation or not in the initial portion of their output characteristics. It is observed that larger drain voltages result in band-to-band tunneling of the electrons occurring from the valance band of the channel to the conduction band of the drain, which causes such sudden increase of drain current. © 2012 The Japan Society of Applied Physics.

Japanese Journal of Applied Physics

Observation of current enhancement due to drain-induced drain tunneling in tunnel field-effect transistors

Fulltext

Indian Journal of Science and Technology

Tunnel Field Effect Transistors for Digital and Analog Applications: A Review

Detailed investigation, with the help of extensive device simulations, of the effects of varying the dielectric constant k of the gate dielectric on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper. It is observed that the fringing field arising out of a high-k gate dielectric degrades the device performance of a p-TFET, which is in contrast with its n-channel counterpart of a similar structure, where the same has been reported to yield better performance. The impact of the fringing field is found to be larger for a p-TFET with higher source doping. It is also found that the qualitative nature of the impact of the fringing field does not change with dimension scaling. On the other hand, the higher electric field due to increased oxide capacitance is found to be beneficial for a p-TFET when a high-k gate dielectric is used in it, as expected. It is also found that a low-k spacer is beneficial for a p-TFET, similar to that reported for an n-TFET of similar structure.

The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High-k Gate Dielectric

A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low-κ dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (∼30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gatesource overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high-κ spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it. © 2011 IEEE.

Impact of a spacer dielectric and a gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-mV/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal-oxide- semiconductor field-effect transistor, particularly for low-power applications. It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not. A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time. It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used. A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltages. © 2011 IEEE.

Drain-dependence of tunnel field-effect transistor characteristics: The role of the channel

Germanium-Source Tunnel Field Effect Transistors for Ultra-Low Power Digital Logic

A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap structures. Performance improvements are illustrated and explained for SiO2, Al 2O3, and HfO2 gate dielectrics. The structure is optimized for the on-state current without degrading the off-state current or the subthreshold slope. © 2006 IEEE.

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ISSN	0018-9383