DEBASRI SAHA

GENERAL

S SUR-KOLAY

University of Calcutta (informally known as Calcutta University or CU) is a collegiate public state university located in Kolkata, West Bengal, India.&nbsp;Within India it is recognized as a &quot;Five-Star University&quot; and accredited &quot;A&quot; Grade by National Assessment and Accreditation Council.

&nbsp;

The University of Calcutta has secured the Fifth position among the Universities of India in the prestigious &quot;Indian University Ranking 2019&quot; list, released by the NIRF of the Ministry of Human Resource Development, Government of India.

&nbsp;

It was established on 24 January 1857, and was one of the first institutions in Asia to be established as a multidisciplinary and Western-style university. Its alumni and faculty include several heads of state, heads of government, social reformers, prominent artists, only academy award winner and Dirac medal winner in India, many Fellows of the Royal Society and five Nobel laureates as of 2019 which is highest in South Asia.

University Of Calcutta

Trusted sharing of intellectual property in electronic hardware design

Proceedings of the 9th Workshop on Embedded Systems Security, WESS 2014

A manufacture-ready layout is vulnerable to misappropriation when it is either fabricated as a chip in a fabrication facility, or reused in a system-on-chip house. We propose an intellectual property protection (IPP) scheme IPPMRL for protection of manufacture-ready layout against unauthorized reuse and inclusion of Trojans. The IPPMRL inserts watermarks in the layout according to designer's signature with an effect of tuning the delays at selected scan flip-flops. Certain dummy fills are reoriented in the neighborhood of selected net segments and it causes fine tuning of delay; certain other selected net segments are resized for coarse change in delay. The IPPMRL not only verifies the watermark in the layout, but also captures its effect as delay fault-induced responses from the packaged chips, fabricated from the watermarked layout, by applying a faster test clock. Due to the controlled effect of watermarking on delay, responses are resilient against process and temperature variation, but capable of detecting hardware Trojan. The method is adaptive to device aging. The results for ISCAS'85 and ISCAS'89 benchmark circuits show that the overhead of watermarking on circuit delay is less than 0.05% and the probability of true false or false true can be at most ∼ 10-6. © 2015 IEEE.

Journal	Data powered by TypesetProceedings of the 9th Workshop on Embedded Systems Security, WESS 2014
Publisher	Data powered by TypesetAssociation for Computing Machinery, Inc
Open Access	No