Detailed investigation, with the help of extensive device simulations, of the effects of varying the dielectric constant k of the gate dielectric on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper. It is observed that the fringing field arising out of a high-k gate dielectric degrades the device performance of a p-TFET, which is in contrast with its n-channel counterpart of a similar structure, where the same has been reported to yield better performance. The impact of the fringing field is found to be larger for a p-TFET with higher source doping. It is also found that the qualitative nature of the impact of the fringing field does not change with dimension scaling. On the other hand, the higher electric field due to increased oxide capacitance is found to be beneficial for a p-TFET when a high-k gate dielectric is used in it, as expected. It is also found that a low-k spacer is beneficial for a p-TFET, similar to that reported for an n-TFET of similar structure.

ABHIJIT MALLICK

Electronic Science

AVIK CHATTOPADHYAY

University of Calcutta (informally known as Calcutta University or CU) is a collegiate public state university located in Kolkata, West Bengal, India.&nbsp;Within India it is recognized as a &quot;Five-Star University&quot; and accredited &quot;A&quot; Grade by National Assessment and Accreditation Council.

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The University of Calcutta has secured the Fifth position among the Universities of India in the prestigious &quot;Indian University Ranking 2019&quot; list, released by the NIRF of the Ministry of Human Resource Development, Government of India.

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It was established on 24 January 1857, and was one of the first institutions in Asia to be established as a multidisciplinary and Western-style university. Its alumni and faculty include several heads of state, heads of government, social reformers, prominent artists, only academy award winner and Dirac medal winner in India, many Fellows of the Royal Society and five Nobel laureates as of 2019 which is highest in South Asia.

University Of Calcutta

The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High- $\kappa$ Gate Dielectric

IEEE Transactions on Electron Devices

A tunnel field-effect transistor (FET) (TFET), in which the dominant carrier tunneling occurs in a direction that is in line with the gate electric field, shows great promise for sub-0.6-V operation. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer-drain overlap on the device characteristics of such silicon TFET is reported in this paper. It is demonstrated that a supersteep subthreshold swing and a significantly reduced off-state current I\rm OFF can be achieved by appropriate designing of the spacer-drain overlap. An investigation of the influence of the drain potential on the device characteristics reveals that the absence of a tunnel-resistance limited region results in long-channel metal-oxide-semiconductor FET-like output characteristics for such a structure. Short-channel effects, such as drain-induced barrier lowering, are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported. © 1963-2012 IEEE.

Impact of a spacer-drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling

In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications, such as transconductance g m, transconductance-to-drive current ratio g m/I D, drain resistance R O, intrinsic gain, and unity-gain cutoff frequency f T, are studied for DG n-TFET, with the help of a device simulator, and compared with that for a similar DG n-MOSFET. Although g m is lower, g m/I D is found to be higher in TFET, except for small values of the gate overdrive voltage, indicating that a TFET can produce higher gain at the same power level than a MOSFET. An extremely high R O and, hence, a high intrinsic gain are also observed for a TFET as compared with that for a MOSFET. A complementary TFET amplifier is found to have more than one order of magnitude higher voltage gain than its MOS counterpart. It is also demonstrated that the drain resistance and, hence, the device gain significantly degrade for increasing body thickness of a TFET. © 2006 IEEE.

Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications

In this paper, the impact of a spacer-drain overlap on the subthreshold characteristics is studied for a silicon n-channel tunnel field-effect transistor, in which the dominant carrier tunneling occurs in a direction that is in-line with the gate electric-field. It is demonstrated that subthreshold swing is significantly reduced by reducing the impact of fringe-induced barrier lowering by appropriate designing of the drain-side spacer. Short-channel effects, such as drain-induced barrier lowering (DIBL), are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported. © 2012 IEEE.

2012 International Conference on Emerging Electronics, ICEE 2012

Spacer-drain overlap dependence of subthreshold characteristics for tunnel field-effect transistors based on vertical tunneling

A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low-κ dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (∼30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gatesource overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high-κ spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it. © 2011 IEEE.

Impact of a spacer dielectric and a gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

Germanium-Source Tunnel Field Effect Transistors for Ultra-Low Power Digital Logic

Applied Physics Letters

Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric

A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap structures. Performance improvements are illustrated and explained for SiO2, Al 2O3, and HfO2 gate dielectrics. The structure is optimized for the on-state current without degrading the off-state current or the subthreshold slope. © 2006 IEEE.

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ISSN	0018-9383