Detailed investigation, with the help of extensive device simulations, of the effects of varying the dielectric constant k of the gate dielectric on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper. It is observed that the fringing field arising out of a high-k gate dielectric degrades the device performance of a p-TFET, which is in contrast with its n-channel counterpart of a similar structure, where the same has been reported to yield better performance. The impact of the fringing field is found to be larger for a p-TFET with higher source doping. It is also found that the qualitative nature of the impact of the fringing field does not change with dimension scaling. On the other hand, the higher electric field due to increased oxide capacitance is found to be beneficial for a p-TFET when a high-k gate dielectric is used in it, as expected. It is also found that a low-k spacer is beneficial for a p-TFET, similar to that reported for an n-TFET of similar structure.