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Study of LER/LWR induced VT variability of an EδDC n-channel MOS transistor
Published in Institute of Electrical and Electronics Engineers Inc.
Pages: 685 - 689
In this paper we present a simple model to study the threshold voltage variability due to line edge roughness (LER) for an n-channel EδDC MOS transistor. The concept of propagation of variance is utilized here. Impact of variation in rms amplitude and correlation length of edge fluctuation on threshold voltage variability is studied. The model is verified with calibrated technology computer aided design (TCAD) simulation results. Impact of channel engineering for reduction of LER induced threshold voltage variability is studied in detail. © 2017 IEEE.