In this paper we present a simple model to study the threshold voltage variability due to line edge roughness (LER) for an n-channel EδDC MOS transistor. The concept of propagation of variance is utilized here. Impact of variation in rms amplitude and correlation length of edge fluctuation on threshold voltage variability is studied. The model is verified with calibrated technology computer aided design (TCAD) simulation results. Impact of channel engineering for reduction of LER induced threshold voltage variability is studied in detail. © 2017 IEEE.

SOUMYA PANDIT

Radio Physics and Electronics

S SENGUPTA

University of Calcutta (informally known as Calcutta University or CU) is a collegiate public state university located in Kolkata, West Bengal, India.&nbsp;Within India it is recognized as a &quot;Five-Star University&quot; and accredited &quot;A&quot; Grade by National Assessment and Accreditation Council.

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The University of Calcutta has secured the Fifth position among the Universities of India in the prestigious &quot;Indian University Ranking 2019&quot; list, released by the NIRF of the Ministry of Human Resource Development, Government of India.

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It was established on 24 January 1857, and was one of the first institutions in Asia to be established as a multidisciplinary and Western-style university. Its alumni and faculty include several heads of state, heads of government, social reformers, prominent artists, only academy award winner and Dirac medal winner in India, many Fellows of the Royal Society and five Nobel laureates as of 2019 which is highest in South Asia.

University Of Calcutta

Study of LER/LWR induced V T variability of an EδDC n-channel MOS transistor

Proceedings of 2nd International Conference on 2017 Devices for Integrated Circuit, DevIC 2017

Conventional planar transistor shows shrinking substrate bias effect at scaled technology. On the other hand, epitaxial delta-doped channel (EδDC) transistor shows substantial amount of substrate bias effect even at 16-nm channel length. This paper unveils the physics behind the substrate bias effect of an n-channel EδDC transistor through Technology Computer Aided Design simulation with analytical justifications. The depletion width for an EδDC transistor very weakly depends upon the applied substrate bias, and with scaling down of channel length, the depletion width insignificantly gets widened. The substrate control over the channel is high so that significant amount of substrate depletion charge terminates on the gate, instead of on the source and the drain. The degradation of threshold voltage roll off and drain-induced barrier lowering coefficient with the increase of substrate bias, is less for the EδDC transistor, compared to that of a conventional halo free transistor. The dependence of the substrate bias sensitivity on the thickness of the low-doped epitaxial layer and concentration of the high-doped layer is explored. The effects of reverse substrate bias on leakage power dissipation and intrinsic delay of EδDC and conventional transistors are discussed. © 2016 Informa UK Limited, trading as Taylor & Francis Group.

International Journal of Electronics

Substrate bias effect of epitaxial delta-doped channel MOS transistor for low-power applications

In this paper, we present a systematic procedure for the design of a channel profile of an epitaxial delta doped channel (EδDC) MOS transistor so that the intrinsic gain (Av) is high and the threshold voltage (VT) mismatch is low. Analytical study shows that a tradeoff relation exists between low VT mismatch and high AV with respect to the thickness of the channel region. Therefore, careful selection of the design parameters is essential in order to have an optimum performance. The performance characteristics of the designed device are subsequently verified through Technology Computer Aided Design simulations. In order to demonstrate the benefits of using optimized EδDC transistor, we compare its performance with that of a reference deeply depleted channel MOS transistor. The performance improvement of using optimized EδDC transistor with respect to the chosen objectives is clearly explained. © 2016 IEEE.

IEEE Transactions on Electron Devices

Channel profile design of EÎ´DC MOSFET for high intrinsic gain and low VT mismatch

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor. © 2014 Taylor and Francis.

Journal	Data powered by TypesetProceedings of 2nd International Conference on 2017 Devices for Integrated Circuit, DevIC 2017
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open Access	No