In this paper, the impact of a spacer-drain overlap on the subthreshold characteristics is studied for a silicon n-channel tunnel field-effect transistor, in which the dominant carrier tunneling occurs in a direction that is in-line with the gate electric-field. It is demonstrated that subthreshold swing is significantly reduced by reducing the impact of fringe-induced barrier lowering by appropriate designing of the drain-side spacer. Short-channel effects, such as drain-induced barrier lowering (DIBL), are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported. © 2012 IEEE.