In this paper, the impact of a spacer-drain overlap on the subthreshold characteristics is studied for a silicon n-channel tunnel field-effect transistor, in which the dominant carrier tunneling occurs in a direction that is in-line with the gate electric-field. It is demonstrated that subthreshold swing is significantly reduced by reducing the impact of fringe-induced barrier lowering by appropriate designing of the drain-side spacer. Short-channel effects, such as drain-induced barrier lowering (DIBL), are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported. © 2012 IEEE.

AVIK CHATTOPADHYAY

Radio Physics and Electronics

ABHIJIT MALLICK

Electronic Science

University of Calcutta (informally known as Calcutta University or CU) is a collegiate public state university located in Kolkata, West Bengal, India.&nbsp;Within India it is recognized as a &quot;Five-Star University&quot; and accredited &quot;A&quot; Grade by National Assessment and Accreditation Council.

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The University of Calcutta has secured the Fifth position among the Universities of India in the prestigious &quot;Indian University Ranking 2019&quot; list, released by the NIRF of the Ministry of Human Resource Development, Government of India.

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It was established on 24 January 1857, and was one of the first institutions in Asia to be established as a multidisciplinary and Western-style university. Its alumni and faculty include several heads of state, heads of government, social reformers, prominent artists, only academy award winner and Dirac medal winner in India, many Fellows of the Royal Society and five Nobel laureates as of 2019 which is highest in South Asia.

University Of Calcutta

2012 International Conference on Emerging Electronics, ICEE 2012

Detailed investigation, with the help of extensive device simulations, of the effects of varying the dielectric constant k of the gate dielectric on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper. It is observed that the fringing field arising out of a high-k gate dielectric degrades the device performance of a p-TFET, which is in contrast with its n-channel counterpart of a similar structure, where the same has been reported to yield better performance. The impact of the fringing field is found to be larger for a p-TFET with higher source doping. It is also found that the qualitative nature of the impact of the fringing field does not change with dimension scaling. On the other hand, the higher electric field due to increased oxide capacitance is found to be beneficial for a p-TFET when a high-k gate dielectric is used in it, as expected. It is also found that a low-k spacer is beneficial for a p-TFET, similar to that reported for an n-TFET of similar structure.

IEEE Transactions on Electron Devices

The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High-k Gate Dielectric

A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low-κ dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (∼30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gatesource overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high-κ spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it. © 2011 IEEE.

Journal	Data powered by Typeset2012 International Conference on Emerging Electronics, ICEE 2012
Publisher	Data powered by TypesetIEEE Computer Society