In this work, process induced strain has been incorporated selectively into Si-substrate by growing TiO2 nano-islands on it using vapour-liquid-solid method and the induced strain has been retained by chemically removing the TiO2 nano-islands. The retained strain is quantified by employing pole study method of the electron backscatter diffraction (EBSD) and compared with the similar results obtained from micro-Raman measurements. A very good agreement between the results indicates accuracy of the developed pole study analyses. Both the methods suggest that such a low-cost approach is capable of incorporating and retaining a compressive strain &gt;4.7% along(100) and tensile strain &gt;1.3% along (010) and (001) directions by growing the crystalline TiO2 nano-islands on Si substrates followed by their chemical removal. © 2017 IOP Publishing Ltd.

SANATAN CHATTOPADHYAY

Electronic Science

M PALIT

B N CHOWDHURY

A DAS

S DAS

University of Calcutta (informally known as Calcutta University or CU) is a collegiate public state university located in Kolkata, West Bengal, India.&nbsp;Within India it is recognized as a &quot;Five-Star University&quot; and accredited &quot;A&quot; Grade by National Assessment and Accreditation Council.

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The University of Calcutta has secured the Fifth position among the Universities of India in the prestigious &quot;Indian University Ranking 2019&quot; list, released by the NIRF of the Ministry of Human Resource Development, Government of India.

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It was established on 24 January 1857, and was one of the first institutions in Asia to be established as a multidisciplinary and Western-style university. Its alumni and faculty include several heads of state, heads of government, social reformers, prominent artists, only academy award winner and Dirac medal winner in India, many Fellows of the Royal Society and five Nobel laureates as of 2019 which is highest in South Asia.

University Of Calcutta

Materials Research Express

In the current work, a design space for developing the performance enhanced strain-engineered Si nanowire field-effect-transistors has been provided. The fraction of insertion of the nanowire channel into the Insulator-on-Silicon substrate with judicious selection of high-k gate insulators is used as the key design parameter. The combined effect of fractional insertion and gate insulators results in inducing stress into the nanowire channel and, depending on their selection, it changes from tensile to compressive. Such induced-stress alters the existing inherent phononic-stress, leading to the modification of the carrier transport in the device channel. The carrier transport behavior in such partially embedded nanowire FETs has been modeled by incorporating the relevant stress-related effects into the indigenously developed self-consistent quantum-electrostatic framework. These equations are solved by employing the non-equilibrium Green's function formalism. The study shows the phonon scattering under tensile strain to occur at the expense of electron energy; however, the electrons can also gain energy during such scattering in compressive stress. Thus, the device current has been observed to increase with tensile stress and it achieves relatively smaller values when the inherent tensile phononic stress is balanced by the induced compressive stress. However, the current is finally observed to increase once the compressive stress overcomes the inherent tensile phononic stress. In general, the present devices exhibit promising I-on/I-off ratio for all of the fractional insertions and gate dielectrics with a maximum I-off of <10 nA/mu m, threshold voltage of sub-0.3 V, g(m) of similar to 10(4) mu S/mu m, sub-threshold swing of similar to 100 mV/dec, and drain-induced-barrier-lowering of similar to 100 mV/V. Published by AIP Publishing.

Fulltext

Journal of Applied Physics

Investigation of the performance of strain-engineered silicon nanowire field effect transistors (epsilon-Si-NWFET) on IOS substrates

The current work proposes a novel technique to incorporate process-induced uni-axial stress for significant mobility boosting in high-performance metal-oxide-semiconductor field-effect-transistors. It has been shown that two existing standard techniques, namely, silicon-on-sapphire and high-k gate dielectrics can be combined to develop such technology. Sapphire has very high elastic constant and thermal expansion coefficient, thereby capable of inducing a significant amount of stress which is observed to be biaxial in nature. However, with the incorporation of different materials during process integration, such biaxial stress is gradually changed to uni-axial nature. The high-k gate dielectric plays the key role in converting the biaxial stress to uni-axial. Several high-k gate dielectrics have been studied and titanium oxide (TiO2) is observed to maximize the induced stress and also effective to convert it to uni-axial. A final average longitudinal channel stress of 0.73 GPa has been obtained. © 2013 IOP Publishing Ltd.

Semiconductor Science and Technology

Estimation of step-by-step induced stress in a sequential process integration of nano-scale SOS MOSFETs with high-k gate dielectrics

Nano Letters

Fully Tunable Silicon Nanowire Arrays Fabricated by Soft Nanoparticle Templating

Nature Nanotechnology

Enhancement of the anisotropic photocurrent in ferroelectric oxides by strain gradients

Nature Communications

Piezoelectric effect in chemical vapour deposition-grown atomic-monolayer triangular molybdenum disulfide piezotronics

Band structure engineering via piezoelectric fields in strained anisotropic CdSe/CdS nanocrystals

Selective strain incorporation and retention into Si-substrate through VLS growth of TiO 2 nano-islands

Journal	Materials Research Express
Publisher	Institute of Physics Publishing
ISSN	2053-1591
Open Access	No