Estimation of decoupling capacitance allocation for noise suppression at pre layout level is the objective of our paper. The experiment is based on the module wise estimation of voltage drop and decoupling capacitance placement. Present trends in VLSI design are inclined towards system on chip (SoC) design. Hence, efficient design plans and CAD approaches should be developed in the SoC domain. We investigate multi-core circuits in our work and consider the custom crypto-cores as example circuits, because they are well used as hardware accelerators in many of the present day application circuits. The novelty in our work lies in the fact that by using our approaches noise can be reduced by 87.23% in an average at the pre-layout stage. Copyright © 2015 American Scientific Publishers All rights reserved.

DEBASRI SAHA

GENERAL

AMLAN CHAKRABORTY

M CHAKRABORTY

K GUHA

P MITRA

University of Calcutta (informally known as Calcutta University or CU) is a collegiate public state university located in Kolkata, West Bengal, India.&nbsp;Within India it is recognized as a &quot;Five-Star University&quot; and accredited &quot;A&quot; Grade by National Assessment and Accreditation Council.

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The University of Calcutta has secured the Fifth position among the Universities of India in the prestigious &quot;Indian University Ranking 2019&quot; list, released by the NIRF of the Ministry of Human Resource Development, Government of India.

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It was established on 24 January 1857, and was one of the first institutions in Asia to be established as a multidisciplinary and Western-style university. Its alumni and faculty include several heads of state, heads of government, social reformers, prominent artists, only academy award winner and Dirac medal winner in India, many Fellows of the Royal Society and five Nobel laureates as of 2019 which is highest in South Asia.

University Of Calcutta

Journal of Low Power Electronics

This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on their power dissipation and proper allocation of decap at the pre-layout level. Decap being in between power and ground distribution networks acts as local charge storage and effectively reduces rapid transients in the supply drop. Therefore, present trends in VLSI design are inclined towards the placement of decoupling capacitors for system on chip (SoC) design. But, early prediction and allocation of decaps at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing power, noise and delay effects for the circuit. The novelty of our work lies in exhaustive module wise estimation of di/dt drop for the complete circuit, followed by an algorithmic estimation and appropriate allocation of decaps with an effort to keep power, delay and noise performance to its best. We choose Double DES as example crypto-core for our test circuits as this is quite complex in nature and are also used as custom cores in many SoC applications. We investigate the change in power, noise and delay parameters with and without the decap allocation for multi-core circuits at the pre-layout stage and find satisfactory suppression of noise at the cost of negligible increase in power and delay. By using our approach, average peak noise and maximum peak noise can be suppressed approximately by 22.7% and 32.23% respectively at the pre-layout stage comparing with the previous works. This early prediction helps in more accurate Computer Aided Design (CAD) implementation at the layout stage. © 2016 IEEE.

Journal	Data powered by TypesetJournal of Low Power Electronics
Publisher	Data powered by TypesetAmerican Scientific Publishers
ISSN	1546-1998
Open Access	No