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Minimization of Drain-End Leakage of a U-Shaped Gated Tunnel FET for Low Standby Power (LSTP) Application
Published in Springer Science and Business Media Deutschland GmbH
Volume: 692
Pages: 393 - 402
In this paper, for the first time, the transfer characteristic of a ‘U’-shaped gated tunnel FET (TFET) has been thoroughly investigated considering the real-time adverse effects of gate-to-drain direct tunneling current and gate-induced drain leakage (GIDL) effect using SILVACO ATLAS device simulator. Clearly, these leakage phenomena degrade the device performance, especially for low standby power (LSTP) operation. Hence, for the first time, a novel design modification has been proposed in terms of the optimization of the oxide thickness (TGD) of right vertical arm of the U-shaped gate, in order to mitigate the aforementioned problem. It has been found that when the TGD value is increased to 7 nm from the equivalent oxide thickness (EOT) value of 1.6 nm, the ultimate device becomes optimized in terms of the performance matrices like, IOFF, SSmin, ION/IOFF, etc. Moreover, 43% reduction in delay and almost 11 decades of OFF-state power reduction have been obtained for the optimized device than that of the device having TGD = 1.6 nm, for gate length of 70 nm. © 2021, The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About the journal
JournalData powered by TypesetLecture Notes in Electrical Engineering
PublisherData powered by TypesetSpringer Science and Business Media Deutschland GmbH