With the enrichment of new technology in the fields of VLSI design and communication there is also a demand of high speed and low area. The aim of this paper is to design a multiplier circuit based on Vedic sutras. The algorithms based on conventional mathematics can be optimized and simplified by using Vedic sutras. In this paper we have given the design up to Multipliers based on Vedic multiplication sutra "Urdhva-Tiryakbhyam" the design of 2×2, 4×4 has been designed in DSCH2 and all the outputs have been given. The layout of those circuits has been also generated by Microwind. The internal circuit diagram of all the blocks has been explained The noise, power have been calculated by T-Spice-13 in 45nm Technology. The hardware has also been implemented in XILINX and tested in Basys™2 Spartan-3E FPGA Board. © 2014 IEEE.