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Fast robust intellectual property protection for VLSI physical design
, S. Sur-Kolay
Published in
Pages: 1 - 6
In deep sub-micron VLSI technology, design reuse has become essential due to more integration on a single chip in shorter time. Design reuse however is susceptible to misappropriation of the Intellectual Property (IP) of the design. There may be illegal reselling or unauthorized reuse of the design, creating false charges on legal buyer by the IP owner, false claim for IP ownership, tampering of watermarks present in the design for IP protection (IPP). While identifying IP owner and legal IP buyer through copy detection remains an exhaustive method, public and convincing watermark verification for IP ownership is not still safe. Our proposed algorithm ROBUST_IP tackles all the problems from an entirely new viewpoint. It facilitates faster extraction of signatures of IP owner and buyer, whereas removing or tampering the watermarks by an attacker remains infeasible, even if public verification is allowed. The scheme is effectively applied for IPP in both ASIC and FPGA designs. It has been tested on various MCNC benchmarks. The experimental results are quite encouraging and the overhead incurred by our technique on the design is negligible. © 2007 IEEE.
About the journal
JournalProceedings - 10th International Conference on Information Technology, ICIT 2007