The current work proposes a novel technique to incorporate process-induced uni-axial stress for significant mobility boosting in high-performance metal-oxide-semiconductor field-effect-transistors. It has been shown that two existing standard techniques, namely, silicon-on-sapphire and high-k gate dielectrics can be combined to develop such technology. Sapphire has very high elastic constant and thermal expansion coefficient, thereby capable of inducing a significant amount of stress which is observed to be biaxial in nature. However, with the incorporation of different materials during process integration, such biaxial stress is gradually changed to uni-axial nature. The high-k gate dielectric plays the key role in converting the biaxial stress to uni-axial. Several high-k gate dielectrics have been studied and titanium oxide (TiO2) is observed to maximize the induced stress and also effective to convert it to uni-axial. A final average longitudinal channel stress of 0.73 GPa has been obtained. © 2013 IOP Publishing Ltd.

SANATAN CHATTOPADHYAY

Electronic Science

S CHATTERJEE

B N CHOWDHURY

A DAS

University of Calcutta (informally known as Calcutta University or CU) is a collegiate public state university located in Kolkata, West Bengal, India.&nbsp;Within India it is recognized as a &quot;Five-Star University&quot; and accredited &quot;A&quot; Grade by National Assessment and Accreditation Council.

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The University of Calcutta has secured the Fifth position among the Universities of India in the prestigious &quot;Indian University Ranking 2019&quot; list, released by the NIRF of the Ministry of Human Resource Development, Government of India.

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It was established on 24 January 1857, and was one of the first institutions in Asia to be established as a multidisciplinary and Western-style university. Its alumni and faculty include several heads of state, heads of government, social reformers, prominent artists, only academy award winner and Dirac medal winner in India, many Fellows of the Royal Society and five Nobel laureates as of 2019 which is highest in South Asia.

University Of Calcutta

Estimation of step-by-step induced stress in a sequential process integration of nano-scale SOS MOSFETs with high-k gate dielectrics

Semiconductor Science and Technology

In the current work, a design space for developing the performance enhanced strain-engineered Si nanowire field-effect-transistors has been provided. The fraction of insertion of the nanowire channel into the Insulator-on-Silicon substrate with judicious selection of high-k gate insulators is used as the key design parameter. The combined effect of fractional insertion and gate insulators results in inducing stress into the nanowire channel and, depending on their selection, it changes from tensile to compressive. Such induced-stress alters the existing inherent phononic-stress, leading to the modification of the carrier transport in the device channel. The carrier transport behavior in such partially embedded nanowire FETs has been modeled by incorporating the relevant stress-related effects into the indigenously developed self-consistent quantum-electrostatic framework. These equations are solved by employing the non-equilibrium Green's function formalism. The study shows the phonon scattering under tensile strain to occur at the expense of electron energy; however, the electrons can also gain energy during such scattering in compressive stress. Thus, the device current has been observed to increase with tensile stress and it achieves relatively smaller values when the inherent tensile phononic stress is balanced by the induced compressive stress. However, the current is finally observed to increase once the compressive stress overcomes the inherent tensile phononic stress. In general, the present devices exhibit promising I-on/I-off ratio for all of the fractional insertions and gate dielectrics with a maximum I-off of <10 nA/mu m, threshold voltage of sub-0.3 V, g(m) of similar to 10(4) mu S/mu m, sub-threshold swing of similar to 100 mV/dec, and drain-induced-barrier-lowering of similar to 100 mV/V. Published by AIP Publishing.

Fulltext

Journal of Applied Physics

Investigation of the performance of strain-engineered silicon nanowire field effect transistors (epsilon-Si-NWFET) on IOS substrates

The combined impact of process-and substrate-induced stress has been analytically modeled for a rectangular fin inserted into an insulator-on-silicon (IOS) substrate. Stress estimation and profiling are performed for different fractional insertion of the fin into the IOS substrate and the induced stress values are observed to saturate for ≥1/3 of the fin insertion. Therefore, a one-Third of inserted Si fin is used to estimate the induced stress by following a standard FinFET process flow. Uniaxial compressive stress as high as 4.6 GPa has been obtained, and it has also been observed that the hole mobility can be enhanced to a significantly high value by judiciously choosing the gate dielectrics and fractional insertion of the fin. Thereby, the design of symmetric CMOS by using such mobility-enhanced p-FinFET is possible. Moreover, the current-voltage characteristics of such strain-engineered p-FinFETs exhibit improved drain-induced barrier lowering and subthreshold swing and 45% enhancement of drain current. © 1963-2012 IEEE.

IEEE Transactions on Electron Devices

Fraction of Insertion of the Channel Fin as Performance Booster in Strain-Engineered p-FinFET Devices with Insulator-on-Silicon Substrate

In the current work, an analytical model has been developed to estimate the amount of induced stress in nanowires which are horizontally embedded with different fractions within an Insulator-on-Silicon substrate. For estimating such stress, different crystallographic orientations of substrates and embedded nanowires have been considered. The induced stress for both the difference in thermo-elastic constants and lattice-mismatch is included and accuracy of the analytical model has been verified with the similar results obtained from ANSYS Multiphysics. Induced stress is observed to be insensitive of the nanowire size, however, depends significantly on the fractional insertion of the nanowires. A tensile stress of 1.95 GPa and a compressive stress of −1.0719 GPa have been obtained for the 〈100〉 oriented Si-nanowires. Hole mobility of 850 cm2/Vs can be achieved for the 3/4th insertion of the nanowires which is comparable to electron mobility and therefore can be utilized for the design of symmetric nano-electronic devices. © 2016 Elsevier Ltd

Superlattices and Microstructures

Analytical modeling of the lattice and thermo-elastic coefficient mismatch-induced stress into silicon nanowires horizontally embedded on insulator-on-silicon substrates

In this work, process induced strain has been incorporated selectively into Si-substrate by growing TiO2 nano-islands on it using vapour-liquid-solid method and the induced strain has been retained by chemically removing the TiO2 nano-islands. The retained strain is quantified by employing pole study method of the electron backscatter diffraction (EBSD) and compared with the similar results obtained from micro-Raman measurements. A very good agreement between the results indicates accuracy of the developed pole study analyses. Both the methods suggest that such a low-cost approach is capable of incorporating and retaining a compressive strain &gt;4.7% along(100) and tensile strain &gt;1.3% along (010) and (001) directions by growing the crystalline TiO2 nano-islands on Si substrates followed by their chemical removal. © 2017 IOP Publishing Ltd.

Materials Research Express

Selective strain incorporation and retention into Si-substrate through VLS growth of TiO 2 nano-islands

This work proposes a novel technique for incorporating a substantial amount of process-induced stress in the channel of FinFET structures. The strain has been incorporated in the channel by choosing FET-constituting materials with appropriate lattice mismatch and thermo-elastic constants. The generated strain/stress remains uniform and sufficiently in-plane uni-axial in nature throughout all the three channels of the FinFET. The resulting stress as high as 1.5GPa has been achieved. © 2015 IEEE.

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ISSN	0268-1242