In this paper, a technique for implementing low-power Dual Edge Triggered Flip Flop (DETFF) is introduced. Dual edge triggered flip flops has many advantages in low power VLSI compared to SETFF. The Proposed low power DETFF is implemented and compared with conventional DETFF at same simulation conditions. CAD tool based simulation and comparison between the non-conventional DET flip-flop with the conventional DETFF shows that the proposed DETFF reduces power dissipation by 66% reducing the no. of transistors used while keeping the same data rate. © 2017 IEEE.