In modern trend, as we are moving for niche devices power managing is a serious anxiety for all handy electronic gadgets. The performance of the device depends highly on temperature profile, which changes rapidly with high power consumption. As most of the devices run by the digital signal processor, the power consumption of DSP chip is the main concern. In the majority of the signal processing algorithms, multiplication operation dominates other operations. Hence in modern low power VLSI design one of the major challenges is to design an efficient multiplier block. In this paper, a low power GDI based radix-4 modified Booth-Wallace multiplier has been projected. CAD tool based simulation shows 35% reduction in power consumption compared to other existing designs. © 2018 IEEE.