This paper proposes an efficient hardware architecture for the spectral subtraction algorithm applied to speech enhancement. Spectral subtraction algorithm is widely used in audio de-noising applications. The proposed architecture uses a novel approach to estimate environmental noise from speech adaptively. After estimating the noise from the input speech the noise samples are subtracted, making it noise free. In this design we have two principal blocks, the noise estimation-subtraction block and the phase block, which are executed concurrently exploiting the parallel logic blocks of field programmable gate array (FPGA). We have implemented our design on Spartan6 LX45 FPGA, which also meets the high speed requirements. Resource utilization and delay information for the different blocks in our design are presented. Our proposed hardware implementation shows a better SNR value compared to the original software implementation. To the best of our knowledge, this work is the first of its kind of implementation in regards to FPGA based hardware design for adaptive noise filtering in speech.