Get all the updates for this publication
Conferences
Aspects and Reduction of Miller Capacitance of Lateral Tunnel FETsPublished in Institute of Electrical and Electronics Engineers Inc.
2018
This paper discusses aspects of gate-To-drain capacitance (Miller capacitance) of lateral tunnel FETs (LTFETs). It is considered how to reduce the mirror capacitance of LTFET. © 2018 IEEE.
Topics: Capacitance (60)%60% related to the paper
View more info for "Aspects and Reduction of Miller Capacitance of Lateral Tunnel FETs"
Content may be subject to copyright.
About the journal
| Journal | Data powered by TypesetIMFEDK 2018 - 2018 International Meeting for Future of Electron Devices, Kansai |
|---|---|
| Publisher | Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc. |
Authors (1)
ABHIJIT MALLICK- A surface potential based subthreshold drain current model for short-channel MOS transistors
- A possible threshold voltage definition of lateral tunnel FET
- A two-dimensional surface potential based subthreshold-slope model for short-channel MOS transistors
- Impact of different barrier layers and indium content of the channel on the analog performance of InGaAs MOSFETs
