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Architecture- and Gate-Oxide-Level Optimization of a Si-Based Asymmetric U-TFET for Low Power Operation: a Real-Time Gate/Drain Electrostatic Based Leakage Perspective
Das S., Chattopadhyay A.,
Published in Springer Science and Business Media B.V.
In this paper, for the first time, an optimized asymmetric U-shaped TFET, suitable for low power application, has been proposed after a hardcore performance analysis, considering the real-time adverse effect of gate/drain leakage phenomena known for deteriorating the subthreshold behaviour of a TFET. Two-level optimization – device-architecture level and gate-oxide level – remains the key factor of the work, ensuring its applicability even under extreme low power. For the proposed device with SiO2 as the material for asymmetric oxide arm, 7 nm turns out to be the optimized thickness, whereas it drops down to 5 nm and 4 nm, respectively, for Al2O3 and HfO2 arms. After a rigorous performance analysis, in terms of OFF-current, ON-current-OFF-current ratio, IDS-range for sub-60-mV/decade subthreshold swing, footprint, footprint-delay product, power-delay product, footprint-leakage-power density, the asymmetric TFET device with 5-nm asymmetric oxide arm of Al2O3 is found to be the most optimized device for the low power operation. © 2022, The Author(s), under exclusive licence to Springer Nature B.V.
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