The design outsourcing of the IC supply chain across the globe has been witnessed as a major trend of the semiconductor design industry in the recent era. The increasing profit margin has been a major boost for this trend. However, the vulnerability of the introduction of malicious circuitry (Hardware Trojan Horses) in the untrusted phases of chip development has been a major deterrent in this cost effective design methodology. Analysis, detection and correction of such Trojan Horses have been the point of focus among researchers over the recent years. In this work, analysis of a secret key revealing Hardware Trojan Horse is performed. This Trojan Horse creates a conditional path delay to the resultant output of the cryptocore according to the stolen bit of secret key per iteration. The work has been extended from the RTL design stage to the pre fabrication stage of ASIC platform where area and power analysis have been made to distinguish the affected core from a normal core in 180nm technology node. © Springer International Publishing Switzerland 2015.