With the progress in VLSI technology increase in circuit density is obvious. In present integrated circuits, electrical power is distributed to the large number of components of the chip over a network of on chip conductors. The systematic arrangement of the power distribution network (PDN) is commonly termed as power grid. The challenge of efficient PDN design escalates to a greater extent especially in the case of embedded system hardware design as they have a very low power budget as well as needs to have a high reliability. In many of the present day computer-aided design (CAD) tools, PDN modeling and analysis are not performed due to lack of proper libraries, designers estimate the PDN in a case to case basis. Our research aims to create suitable models for PDN extraction so that it can be addressed by the CAD tools. We consider the cryptocores for PDN analysis as they are complex as well as are used in a wide range of applications. Our experimental results show 0.03% and 0.142% increments in power dissipation in DES and in AES respectively after inclusion of PDN circuitry. PDN analysis for custom application cores is not available in related research works and hence our work can serve as state of the art benchmarks for PDN. © 2014 IEEE.