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An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidance
Published in Institute of Electrical and Electronics Engineers Inc.
Pages: 1 - 6
These days, in emergency, multiple assay operations are required to be performed at parallel. Area of a given chip as a constraint, how efficiently we can use the chip and how much parallelism can be built-in are the objectives of this paper. A typical application of an assay may characterize a sample where, say only one type of reagent and multiple samples have been considered, or vice versa, and identify some factor(s) of the sample(s) under requirement in parallel. A generalized application may also consider more samples and more reagents for respective findings at parallel. In our experimentation, we effectively do this task in parallel for five such sets of sub regions of a given restricted sized chip in Digital microfluidics using an array based partitioning pin assignment technique, where cross contamination problem has also been considered, and efficiency of proper taxonomy of a given sample has also been improved. © 2015 IEEE.
About the journal
JournalData powered by Typeset19th International Symposium on VLSI Design and Test, VDAT 2015 - Proceedings
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo