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A reconfigurable memory-based fast VLSI architecture for computation of the histogram
, S BANERJEE
Published in Institute of Electrical and Electronics Engineers Inc.
2019
Volume: 65
   
Issue: 2
Pages: 128 - 133
Abstract
Histogram computation is a fundamental task often encountered in image processing systems. This plays an important role in various applications like image registration, show-through correction method in scanned image of duplex mode printed document, etc. Mutual information (MI) is one of the best metric for intensity-based multimodality image registration. Similarity measurement between the images consumes significant amount of the execution time in image registration. Computation of MI requires to obtain individual and joint histogram of two images. Typical joint histogram sizes range between 32 2 and 256 2 . The demand of hardware resource for computation of histogram increases substantially with increasing of histogram size. The array-based method may not be a suitable candidate in this application, because of large histogram size. Computation of histogram is inherently sequential in nature. But a parallel computation of histogram would reduce the processing time, which is going to help various imaging systems. In this paper, a memory-based parallel algorithm for histogram computation and its possible VLSI architecture have been presented. The architecture is mapped in field programmable gate array. The proposed architecture utilizes 99.66% less of the hardware compared to latest available architecture in the literature and consumes 8.78 mW power. © 1975-2011 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Consumer Electronics
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN0098-3063