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A new efficient topological structure for floorplanning in 3D VLSI physical design
A.K. Khan, R. Vatsa, S. Roy,
Published in IEEE Computer Society
2014
Pages: 696 - 701
Abstract
Floorplanning is a key problem in VLSI physical design. The floorplanning problem can be formulated as that a given set of 3D rectangular blocks while minimizing suitable cost functions. Here, we are concentrating on the minimization of the total volume of 3D die. In this paper, first we propose a new topological structure using weighted directed graph of a floorplaning problem in 3D VLSI physical design. But here the main question is this structure is effective or not. For this, we give the idea of a new algorithm to minimize the volume of 3D die in floorplanning problem using this new representation technique. It is interesting to see that our proposed structure is also capable to calculate the total volume and position of the dead spaces if dead spaces exist. Next, we give the experimental result of our new algorithm and then conclude the paper. © 2014 IEEE.
About the journal
JournalData powered by TypesetSouvenir of the 2014 IEEE International Advance Computing Conference, IACC 2014
PublisherData powered by TypesetIEEE Computer Society