Minimization of total (vertical) wire length in VLSI physical design automation is one of the most important topics of current research. As fabrication technology advances, devices and interconnection wires are placed in closer proximity and circuits operate at higher frequencies. At the same time, delay is a factor that suspends in conveying a desired signal to its destination in proper time. This factor is directly proportional to the length of the interconnecting wire segments involved. Pal et al developed a. purely graph theoretic framework, designated as TAH (track assignment heuristic), for computing routing solutions using minimum possible area. In this paper we compute routing solutions with reduced total wire length using the TAH framework. The algorithm is used for computing two-layer no-dogleg routing solutions for most of the well-known benchmark channels. Performance of our algorithm is highly encouraging.