The guard zone computation problem finds immense applications in the field of VLSI physical design automation and design of embedded systems, where one of the major purposes is to find an optimized way to place a set of two-dimensional blocks on a chip floor. In VLSI layout design, the circuit components (or the functional units / modules or groups / blocks of different sub-circuits) that may be viewed as a set of polygonal regions on a two-dimensional plane, are not supposed to be placed much closer to each other in order to avoid electrical (parasitic) effects among them . Each (group of) circuit component(s) Ci is associated with a parameter δi such that a minimum clearance zone of width δi is to be maintained around Ci. If the guard zonal regions overlap, we have to remove the overlapped regions in order to compute the resultant outer guard zone (sometimes inner guard zones are also an issue to be considered). The location of the guard zone (of specified width) for a simple polygon is a very important problem for resizing the (group of) circuit components. In this paper, we have developed an algorithm to compute the guard zone of a simple polygon as well as to exclude the overlapped regions among the guard zonal segments (if any) in O(n log n) time, where n is the number of vertices of the given simple polygon. © 2014 IEEE.