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A 2D Guard Zone Computation Algorithm for Reassignment of Subcircuits to Minimize the Overall Chip Area
Published in Springer Verlag
Volume: 305 AISC
Issue: VOLUME 2
Pages: 183 - 209
The guard zone computation problem finds vast applications in the field of VLSI physical design automation and design of embedded systems, where one of the major purposes is to find an optimized way to place a set of 2D blocks on a chip floor. In VLSI layout design, the circuit components (or the functional units/modules or groups/blocks of different subcircuits) are not supposed to be placed much closer to each other in order to avoid electrical (parasitic) effects among them (http://en.wikipedia.org/wiki/Curve_orientation, [13]). The (group of) circuit components on a chip floor may be viewed as a set of polygonal regions on a two-dimensional plane. Each (group of) circuit component(s) C i is associated with a parameter δ i such that a minimum clearance zone of width δ i is to be maintained around C i. The regions representing the (groups of) circuit components are in general isothetic polygons, but may not always be limited to convex ones. The location of the guard zone (of specified width) for a simple polygon is a very important problem for resizing the (group of) circuit components. In this paper, we have developed an algorithm to compute the guard zone of a simple polygon as well as to exclude the overlapped regions among the guard zones, if any. If the number of vertices in the given polygon is n, then our algorithm requires O(n log n + I log n) time, where I is the number of intersections among the guard zones. So, it is output sensitive in nature that depends on the value of δ i. The algorithm developed in the paper is proved to report a preferred guard zone of the given simple polygon excluding all the intersections, if any. © Springer India 2015.
About the journal
JournalData powered by TypesetAdvances in Intelligent Systems and Computing
PublisherData powered by TypesetSpringer Verlag
Open AccessNo